FIFOEN=UARTN_FIFOS_ARE_DISA, RXTRIGLVL=TRIGGER_LEVEL_0_1_C, RXFIFORES=NO_IMPACT_ON_EITHER_, TXFIFORES=NO_IMPACT_ON_EITHER_
FIFO Control Register. Controls UART FIFO usage and modes.
| FIFOEN | FIFO Enable. 0 (UARTN_FIFOS_ARE_DISA): UARTn FIFOs are disabled. Must not be used in the application. 1 (ACTIVE_HIGH_ENABLE_F): Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. |
| RXFIFORES | RX FIFO Reset. 0 (NO_IMPACT_ON_EITHER_): No impact on either of UARTn FIFOs. 1 (WRITING_A_LOGIC_1_TO): Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. |
| TXFIFORES | TX FIFO Reset. 0 (NO_IMPACT_ON_EITHER_): No impact on either of UARTn FIFOs. 1 (WRITING_A_LOGIC_1_TO): Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. |
| DMAMODE | DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 20.6.6.1. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXTRIGLVL | RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. 0 (TRIGGER_LEVEL_0_1_C): Trigger level 0 (1 character or 0x01). 1 (TRIGGER_LEVEL_1_4_C): Trigger level 1 (4 characters or 0x04). 2 (TRIGGER_LEVEL_2_8_C): Trigger level 2 (8 characters or 0x08). 3 (TRIGGER_LEVEL_3_14_): Trigger level 3 (14 characters or 0x0E). |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |